This invention relates to an art of a semiconductor integrated circuit and, more particularly, to the semiconductor integrated circuit which compensates a base current for realizing high input resistance.
A conventional method of enhancing input resistance of a semiconductor integrated circuit has been used by which the base current is compensated.
The method of compensating the base current has been disclosed in the Japanese Patent Laid-open No. 169108 (1991).
FIG. 2 shows a circuit of the aforementioned prior art.
Referring to FIG. 2, reference codes 21 and 25 to 28 denote NPN transistors. Reference codes 22 to 24 and 29 denote PNP transistors. Reference codes 30 and 31 denote diodes. Reference codes 32 and 33 denote constant current sources. Reference codes 34 and 35 denote resistors.
In FIG. 2, a high voltage power is supplied by a terminal 53. A low voltage power is supplied by a terminal 56. Terminals 51 and 52 are used as input terminals. Terminals 54 and 55 are used as output terminals.
Supposing that the current amplification factor of NPN transistors 21 and 25 to 28 is .beta. and a current amplification factor of PNP transistors 22 to 24 and 29 is .beta.', and a current from the constant current source 33 is I.sub.1, base currents i.sub.7 and i.sub.8 of the NPN transistors 27 and 28 are derived from the following equation (1) when input voltage between terminals 51 and 52 measures 0. ##EQU1##
If the current of the constant current source 32 is set to I.sub.1 in the same manner as the constant current source 33, a base current i.sub.1 of the NPN transistor 21 is derived from the following equation (2). ##EQU2##
The PNP transistors 22 to 24 and 29 form a current mirror circuit. If those PNP transistors 22 to 24 and 29 are provided with the same characteristics, collector currents i.sub.2, i.sub.3 and i.sub.9 of the PNP transistors 22, 23 and 29, respectively are derived from the following equation (3). ##EQU3##
Base currents i.sub.5 and i.sub.6 from the NPN transistors 25 and 26, respectively are derived from the following equation (4). ##EQU4##
An input bias current I.sub.B at each of the terminals 52 and 53 is derived from the equation (5). ##EQU5##
If the current amplification factors .beta. and .beta.' are set to preset values, the bias current is minimized and high input resistance is realized.